Freescale, STMicro partnership focuses on safety

  • 19-Jan-2010 06:18 EST
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Freescale and STMicro are designing chips for safety applications, using international safety regulations that many automakers are adopting.


The joint partnership between Freescale Semiconductor and STMicroelectronics has unveiled a dual-core microcontroller that is focused on safety applications and meets international safety standards.

The MPC564xL and SPC56EL house two 32-bit Power Architecture cores with up to one megabyte of flash memory and a number of peripherals. The devices are designed specifically for safety applications for which reliability is mandatory. Both companies will market the chip, which was developed through their joint development program formed in early 2006.

They address that requirement by meeting two key regulations used for products with high safety integrity level demands. The standards, International Electrotechnical Commission 61508 and International Organization for Standardization 26262, are being applied to many safety-critical systems.

“The increasing importance of safety systems in cars, including advanced driver assistance and vehicle dynamics control, strengthens the need for more reliable and robust electronics,” said Paul Grimme, Corporate Vice President and General Manager of STMicroelectronics’ Automotive Product Group.

Both processors run at a maximum of 120 MHz. Thomas Boehm, Freescale's Global Marketing Manager, Chassis & Safety Systems, noted that dual cores don’t truly double speed but yield around 1.7 times more performance. That’s equivalent to 200 MHz.

However, more speed improvements are provided by an enhanced core architecture. The device uses two execution units in its pipeline, letting the chip execute two instructions simultaneously. That improves throughput by about 20%, he said.

The line also offers a large number of peripherals optimized for safety and motor-control applications. For example, one peripheral controls two brushless three-phase motors. The peripherals can run at higher clock rates than many parts, even running at different speeds than the core.

“For power consumption, you may want to run the CPU at 80 instead of 120 MHz, but you need resources so you want to run the analog to digital converters or the pulse width modulation unit at 120 MHZ,” said Boehm.

The two cores can run in lockstep or be decoupled. That gives design engineers more freedom, letting them do tasks simultaneously when necessary. The chip also provides a fault collection unit that lets system designers define how certain faults will be dealt with. That lets systems operate in a limp-home mode when their basic functionality has been compromised.

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