Microchip develops compact EEPROM bus

  • 13-May-2008 10:01 EDT
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Microchip’s UNI/O bus is compact yet offers the capabilities of larger interfaces.

Microchip Technology is taking aim at the EEPROM (electrically erasable programmable read-only memory) market, the company developing a new bus architecture and devices that support it.

EEPROM is a small segment of the burgeoning market for nonvolatile memory, which is dominated by flash memory, but it is a critical niche in areas for which only very small capacities are needed.

EEPROM offers byte selectability, which works better in applications where only a small amount of data is written. In contrast, flash must be written in sectors. That takes longer, and it stresses the whole sector, cutting down long-term reliability.

“If you’re reading and writing a lot, endurance is key; EEPROM is 10 to 100 times better,” said Pete Sorrells, Director of Marketing with Microchip’s Memory Products Division. EEPROM is rated at 1 million cycles or higher, while most flash only lasts 100,000 cycles or less.

Those traits fit well in applications such as airbags and antilock brakes, where a small amount of data must be captured before and after activation events. The amount of information being written isn’t large, but it is constantly changing, so the long lifetime of EEPROM is important.

Microchip has developed a new bus designed to optimize performance for these devices.

The UNI/O bus offers the best of inter-integrated circuit (I2c) and serial peripheral interface (SPI) buses. I2c is inexpensive and requires only two pins, but its capabilities are limited. SPI has higher speeds and more features, but it is more expensive. Its cost has limited it to around 10% of the EEPROM market, Sorrells explained.

UNI/O has a peak speed of 100 kHz, typically enough speed for its target applications, Sorrells said. When the microprocessor is busy, the bus can alter that speed to wait on the CPU (central processing unit). The new bus requires only three I/O pins, half the number of many SPI bus implementations.

That compact size is important in many applications for which board space is limited. Using only one line more than power and ground also frees up CPU leads so they can be dedicated to other functions, Sorrells explained.

Microchip is unveiling five new chips that employ the architecture with a maximum capacity of 128 Kbits. “In the EEPROM market, about 70% of the volume is in lower capacity ranges, up to 16 Kbits,” Sorrells said.

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