Overcoming design challenges of next-generation UASs

  • 21-Oct-2013 12:14 EDT
Figure 6.jpg

Electromagnetic interference analysis on chip, package, and board.

Unmanned air systems (UASs) are an example of a smart system that has traditionally been used to provide intelligence, surveillance, and reconnaissance (ISR) functions. However, as the value of UASs continues to be demonstrated in the field, military forces are pushing the evolution of UASs from ISR roles to advanced warfare assignments in more threatening environments.

Concurrently, UASs are also transitioning from the military to civilian sector for domestic security and surveillance operations. Next-generation UASs will require even more performance and must integrate increasing capabilities for guidance control, weaponry, and surveillance—all in a very limited space. This creates challenges for power and thermal management not seen in previous generations of electronic systems.

To be successful, UASs design plans must incorporate advanced power and thermal management strategies from the earliest stages of the design process and assess issues from the component to the system. For smart-system designers, the driving technologies for ensuring power and thermal integrity are low-power design and 3-D integration.

Greater capabilities create new challenges

In the current fiscal environment and to meet the DOD's strategic goals for UAS roll out, lower cost and lower risk platforms need to be developed. UASs must transition seamlessly from one mission requirement to the next with plug-and-play modular payloads supporting joint forces operation and allowing modification for civilian use.

At the same time, the performance of onboard electronics must improve to support advanced sensors and weapons systems. Accompanying these technology developments is an insatiable demand for power that conflicts with platform capability objectives.

For instance, ultra-endurance systems must balance long-term sustained power against the additional weight of power generation and storage systems. Physics-based engineering simulation can be valuable in addressing the challenges of power and thermal management early in the design cycle.

Powering smart UASs

One example of an increasingly smart UAS is the growth in the level of autonomous operation—including automatic takeoff and landing and “swarming” operations jointly with a team of other UAS. The need for autonomous operation adds a layer of complexity to UAS control systems as they require analysis of large amounts of sensor data and complex algorithms for environment detection, situation awareness, decision making, and flight control.

In addition, engineers must meet strict reliability and safety requirements by focusing on the processor chips, sensor images, and storage devices that power the UASs.

Processor chips are undeniably the electronic brains of UASs. However, the design of these chips has become more challenging than before.

Next-generation UASs require low-power optimization to help extend their battery life requirements but still have robust performance capabilities to handle high-processing functions, such as guidance control, weaponry and surveillance—all in a very small form factor. This creates greater challenges for power and thermal management not seen in previous generations of electronic systems.

Autonomous operation, target acquisition, data compression, and other functionalities of UAS control systems require additional compute support and hardware.

Hardware must be designed for low power, to fit into the power envelope of the supply system. Unnecessary power consumption in UAS’ onboard electronics leads to early depletion of battery power and electrical and thermal reliability issues, shortening expected field lifetime.

The first step in smart system power management is optimization of the chip’s power consumption early in the design stage. Given the size and complexity of modern electronics, dedicated power optimization tools are needed to analyze the chip implementation complexity and identify opportunities for power optimization. Reducing component power consumption also reduces the amount of heat it generates, ensuring reliable system operation in its target environment.

As UAS reconnaissance and surveillance application grows, advanced sensor technology is needed to provide capability for higher-resolution images. Sensor functionality is key to enabling autonomous operation of UASs, allowing advanced interaction with the environment (i.e., takeoff and landing).

Fail-safe technology based on advanced sensor systems will be critical for “sense-and-avoid” requirements defined by the FAA to prevent civilian airspace collisions. Sensor chips are sensitive to power-ground noise, and require validation of digital and analog power domains. Analog sensor circuits must be carefully protected from noise coupling through substrate and package to meet high sensitivity requirements.

To achieve low-power targets, embedded low drop-out regulators are typically used in designs requiring accurate device-level modeling and analysis of circuits, silicon substrate, package, and system interactions to verify sensor chip supply integrity.

UASs require memory capacity to support complex missions and collect data in higher resolution during longer missions. As UASs become truly autonomous, control algorithm complexity and the amount of sensor data to be processed increases dramatically, requiring a significant increase in main memory and data storage space.

Likewise, non-volatile memory for storing high-resolution sensory data over long mission duration time increases required storage space. Onboard memory reliability is a concern for UASs since they can experience extreme temperature variations impacting performance. Validation of the memory chip functionality and reliability is necessary, with full-chip capacity and SPICE-level accuracy, to ensure no voltage drop or electromigration violations occur throughout multiple modes of operation.

Analysis tools targeting these designs must strike a balance between supporting large design sizes, device complexity, and current models to achieve the accuracy necessary for design verification, with reasonable analysis time.

Power integrity analysis for onboard electronic systems is needed to verify that total system power supply meets each component’s requirements. For example, unnecessary functional blocks can be deactivated to avoid wasted power and unwanted heat generation. As the mission progresses, new functional blocks are activated while others are deactivated, causing power supply surges.

Full-chip power integrity analysis flows can analyze this ramp-up behavior, including electrical models of the package and board. Power analysis results enable chip, package, PCB, and power supply system optimization.

UAS electronics can be prone to electromagnetic interference (EMI) effects, particularly in hostile space environments. An electronic component radiates electromagnetic energy that is received by other components disturbing operation.

For UAS electronics, high component density and integration with sensitive sensory systems make EMI challenging. For this reason, the U.S. military developed compliance standards for electromagnetic compatibility (EMC).

Controlling EMI and achieving compliance with EMC specifications must be approached from two directions: controlling the emission of electromagnetic energy in each component, and controlling sensitivity to emissions by other components. Major sources of electromagnetic radiation, transient switching of currents, and power delivery network resonance can be suppressed through chip, package, and PCB board supply system design and analysis.

Beating the heat

As electronic components consume power, they generate heat that must be removed to avoid overheating and loss of reliable operation. Effective thermal management, which ensures the functionality of onboard electronics, has become more of a challenge due to the trends toward UAS miniaturization and the demand for more onboard electronics driving up system power and thermal output.

System power dissipation and cooling solutions can be a major bottleneck for miniaturization.

Consequently, thermal management cannot be treated as an afterthought or as a problem to be solved downstream in the design process. It has to be addressed as an integral part of system design. Thermal management requires heat generation and dissipation optimization, involving an understanding of cooling air flow as well as thermal stresses. This makes it a multi-physics problem.

Heat generation linked to power dissipation in the system can be accurately predicted using full-chip power analysis software for single-chip and 3-D stacked-die designs. Advanced thermal modeling software can be used to simulate heat transport in the chip package and cooling mechanisms, and analyze system heat distribution to drive selection of package options and cooling solutions.

Demand for onboard computing capability will grow dramatically as the military seeks to expand UAS systems beyond ISR and into strike capability and longer mission duration, as well as provide defensive capabilities in hostile environments. Deployment of UASs in civilian airspace adds additional requirements on system safety and reliability.

A multi-physics simulation approach initiated early in the design phase can simulate power consumption and thermal dissipation in complex UAS systems, enabling successful power reduction and thermal cooling solutions for onboard electronics.

This article was written for Aerospace Engineering by Rob Harwood, Director of Aerospace and Defense Industry, ANSYS, Inc., and Margaret Schmitt, Area Sales Director, Apache Design, Inc.


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